Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

ABSTRACT

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 12/751,980, now U.S. Pat. No. 8,154,119, entitled “Compliant Spring Interposer for Wafer Level Three Dimensional (3D) Integration and Method of Manufacturing,” filed on Mar. 31, 2010, which is assigned to the assignee hereof and hereby expressly incorporated by reference herein.

FIELD

The invention relates to an interposer module that bridges chips (or wafers) to a substrate and routes interconnection lines. More particularly, the invention relates to a compliant spring interposer for wafer level three dimensional (3D) integration and method of manufacturing the same.

BACKGROUND

An interposer module (also called an interposer wafer) is used to bridge or connect multiple devices, chips or wafers to a substrate. Designing an interposer module is difficult because the interposer module needs to account for different sized and shaped devices having different topologies. Heterogeneous integration requires the interposer module to incorporate different sized and shaped devices that generally have different topologies. For example, the difference in device heights makes the design of the interposer module challenging because the designer needs to adjust the vertical topology of the interposer module to be exactly matched with the device heights. This requires accurate control of the fabrication process.

In addition, the interposer module has limits in selecting bonding methods and requires multiple bonding. Heterogeneous integration generally requires multiple bonding processes. The bonding process becomes more frequent as the number of devices increases. The difficulty becomes more challenging when the devices are stacked in a three-dimensional (3D) orientation.

Existing interposer modules have several drawbacks. For example, the different device topologies have different device heights making it difficult to properly integrate the devices. To modulate the different heights, prior methods involved stacking bump materials or using bonding methods that compress bonding material. However, both methods are difficult because these methods do not allow for accurate control of the fabrication process. Furthermore, even though the device topologies for integration can be adjusted or involves identically designed devices, the device topologies can be diverse because of fabrication variations. This diversity cannot be controlled and the process should be designed to compensate for the unpredictable difference in wafer surface profile, material deposition thickness, material etching rate, wafer bowing, etc.

Another drawback is the number of different bonding processes required for the different devices. Typically, as the number of devices increase, so does the number of bonding processes. The multiple bonding processes involve different bonding steps, materials and conditions such as temperature, pressure, voltage, etc. The sequence of bonding processes should be carefully designed and controlled so that latter bonding methods do not damage former bonding materials and former bonding methods do not generate any issues to disturb the latter bonding conditions. The multiple bonding processes also generate several thermal cycles, which can produce problems such as device stress, wafer bowing, material oxidation, inter-material reaction, outgasing, and material damages.

In some situations, the devices need to be encapsulated to protect them from damage or contamination created by dust, debris, particles, humidity or chemicals. Some applications need a hermetically sealed vacuum package to improve device performance and reliability. These goals are generally achieved by employing additional wafers that cap the devices, which, however, increase fabrication complexity and cost and produce yield problems.

The above drawbacks provide challenges to designers of interposer modules. Thus, there is a need for an interposer module that overcomes the above drawbacks.

SUMMARY

In one embodiment, the present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, objects, and advantages of the invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, wherein:

FIG. 1A is a cross-sectional view of a device and an apparatus that incorporates interposer technology where the apparatus is spaced apart from the device according to an embodiment of the invention;

FIG. 1B is a cross-sectional view of a device and an apparatus that incorporates interposer technology where the apparatus is bonded to the device according to an embodiment of the invention;

FIG. 1C is a cross-sectional view of a device and an apparatus that incorporates interposer technology where the first and second interposer springs are not bonded to but are touching the first and second TSVs and the first and second bumps located on the chip of the device according to an embodiment of the invention;

FIG. 2 is a chart of several bonding materials and their corresponding bonding process according to an embodiment of the invention;

FIGS. 3A-3F are cross-sectional views of a device and an apparatus that incorporates interposer technology according to an embodiment of the invention; and

FIGS. 4A and 4B are cross-sectional views of a device and an apparatus that incorporates interposer technology according to an embodiment of the invention.

DETAILED DESCRIPTION

Apparatus, systems and methods that implement the embodiments of the various features of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate some embodiments of the invention and not to limit the scope of the invention. Throughout the drawings, reference numbers are re-used to indicate correspondence between referenced elements.

FIG. 1A is a cross-sectional view of a device 101 and an apparatus 100 that incorporates interposer technology where the apparatus 100 is spaced apart from the device 101 according to an embodiment of the invention. The apparatus 100 may be positioned on the device 101 as shown in FIG. 1B. The device 101 may include a substrate 102 or a through-silicon via (TSV) wafer 102, first and second TSVs 104 a and 104 b, a chip 106, first and second bumps 108 a and 108 b, and/or first and second lower outer bond rings 110 a and 110 b. The first and second bumps 108 a and 108 b may provide electrical connections to the underlying chip 106. The first and second lower outer bond rings 110 a and 110 b may be a single lower outer bond ring. As shown in FIG. 1A, the heights of the first and second TSVs 104 a and 104 b, the first and second bumps 108 a and 108 b, and the first and second lower outer bond rings 110 a and 110 b are different.

The first and second TSVs 104 a and 104 b are vertical electrical connections which pass completely through the TSV wafer 102. The chip 106 is mounted on the TSV wafer 102. The first and second TSVs 104 a and 104 b and the first and second bumps 108 a and 108 b may be flat or curved and/or flexible. The first and second bumps 108 a and 108 b may be bonded to the chip 106.

The apparatus 100 may include an interposer wafer 112, a cap 114, first and second upper outer bond rings 116 a and 116 b, a first interposer spring assembly 117 a having a first interposer spring 118 a and a first electrical connection 120 a, and a second interposer spring assembly 117 b having a second interposer spring 118 b and a second electrical connection 120 b. In one embodiment, the first and second interposer springs 118 a and 118 b are cantilevered springs or interposer beams. The first and second interposer springs 118 a and 118 b may be formed in the shapes of a cantilevered bridge L shape or curved shape or crab leg shape and are made from a ceramic, a silicon, a metal or a glass material and combinations thereof. The downward force 122 exerted on each interposer spring 118 a or 118 b is greater than the bending force of each interposer spring 118 a or 118 b and less than the fracture force of each interporser spring 118 a or 118 b. The minimum downward force 122 can also be greater than the bonding force needed to bond the first upper outer bonding ring 116 a to the first lower outer bonding ring 110 a. The first and second upper outer bond rings 116 a and 116 b may be a single upper outer bond ring.

The apparatus 100 may be referred to as a compliant interposer. The apparatus 100 can be separately fabricated from the device 101. Thus, the design and fabrication processes for the apparatus 100 can be simplified and decoupled from the device 101. In addition, the apparatus 100 (i.e., the interposer wafer) can be used as a cap 114 or a cover to protect the device 101 from contamination such as dust, debris or particles. The first and second upper outer bond rings 116 a and 116 b may be hermetically bonded to the first and second lower outer bond rings 110 a and 110 b to produce a hermetically packaged apparatus or chip.

FIG. 1B is a cross-sectional view of the device 101 and the apparatus 100 that incorporates interposer technology where the apparatus 100 is bonded to the device 101 according to an embodiment of the invention. As shown in FIG. 1B, the first interposer spring assembly 117 a and the second interposer spring assembly 117 b may gradually bend when each assembly 117 a and 117 b comes into contact with the first and second TSVs 104 a and 104 b, the first and second bumps 108 a and 108 b located on the chip 106 and/or the first and second lower outer bond rings 110 a and 110 b. The bending allows the apparatus 100 to accommodate for the height differences of the components of the device 101 and to provide for good bonding and mechanical and electrical connections.

The first electrical connection 120 a is mechanically connected to the first interposer spring 118 a. The first interposer spring 118 a is capable of bending to allow the first electrical connection 120 a to electrically contact the first TSV 104 a and the first bump 108 a, which is connected to the chip 106. Similarly, the second electrical connection 120 b is connected to the second interposer spring 118 b. The second interposer spring 118 b is capable of bending to allow the second electrical connection 120 b to electrically contact the second TSV 104 b and the second bump 108 b, which is connected to the chip 106. The first and second interposer springs 118 a and 118 b provide an electrical and mechanical bridge to connect the first and second TSVs 104 a and 104 b to the first and second bumps 108 a and 108 b on the chip 106. A larger bonding pressure 122 can be applied to the interposer wafer 112, which is transferred to the TSVs 104 a and 104 b and the first and second bumps 108 a and 108 b, because of the flexibility and bending force of the first and second interposer springs 118 a and 118 b.

The first and second electrical connections 120 a and 120 b are in direct mechanical and electrical contact with the first and second TSVs 104 a and 104 b and the first and second bumps 108 a and 108 b located on the chip 106. Specifically, the first electrical connection 120 a connects the first TSV 104 a to the first bump 108 a and the second electrical connection 120 b connects the second TSV 104 b to the second bump 108 b.

The bonding pads (e.g., the first and second TSVs 104 a and 104 b, the first and second bumps 108 a and 108 b, and/or the first and second lower outer bond rings 110 a and 110 b) are designed to provide good electrical connections and to withstand large bending pressures provided by the interposer wafer 112. The first and second TSVs 104 a and 104 b and the first and second bumps 108 a and 108 b may have a flat or curved surface, or may be formed in the shape of a square, rectangle or oval and/or may be made of a flexible material to allow for good connections to the first and second electrical connection 120 a and 120 b and to avoid any open connections across the TSV wafer 102. The good connections are achieved by adjusting or controlling the height of the bonding pads and/or by utilizing compliant and conductive materials such as soft metals like gold, silver, tin, aluminum or copper. The compliant and conductive materials should not be oxidized and should be chemically stable during processing. For example, copper may quickly become oxidized after deposition but can be encapsulated or plated with a less-oxidizing material such as gold. Hence, the bonding pads can be encapsulated or plated with a less-oxidizing material. Also, the compliant and conductive material should be able to sustain high pressures from the first and second interposer springs 118 a and 118 b, which may induce cracks or fractures.

After the apparatus 100 is pressed onto the device 101, all the TSVs 104 a and 104 b, the first and second bumps 108 a and 108 b, the first and second interposer springs 118 a and 118 b, the first and second electrical connections 120 a and 120 b, the lower outer bond rings 110 a and 110 b, and the upper outer bond rings 116 a and 116 b are simultaneously bonded together in a single bonding step. Hence, all the components are fixed and bonded together at the same time to limit the number of bonding materials, minimize misalignment of the components, reduce the complexity of the fabrication process and increase the reliability of the apparatus 100 after the single step bonding process. The single bonding step includes the appropriate bonding conditions such as temperature, pressure and/or voltage.

FIG. 2 is a chart of several bonding materials and their corresponding bonding process according to an embodiment of the invention. In one embodiment, the bonding process can be set up so that each component bonds one after another. In this embodiment, a different bonding material or process is used for each component. FIG. 2 shows several different bonding materials and processes that can be used for each of the components to produce a bonding process where each component may bond one after another (i.e., in a sequential manner). For example, a sequential bonding process can occur by increasing the bonding temperature from 200 degrees C. to 300 degrees C. so that a first Gold-Indium bond occurs between the lower outer bond rings 110 a and 110 b and the upper outer bond rings 116 a and 116 b, a second Silver-Tin bond occurs between the TSVs 104 a and 104 b and the first and second interposer springs 118 a and 118 b, and a third Nickel-Tin bond occurs between the first and second bumps 108 a and 108 b and the first and second interposer springs 118 a and 118 b. In this example, the highest bonding temperature of 300 degrees C. does not damage the first Gold-Indium bond because of a higher remelt temperature of greater than 495 degrees C. Using a sequential bonding process, the selection of the bonding materials and processes is important so that previously bonded materials are not damaged by subsequent bonding materials in order to maintain good quality bonding.

FIG. 1C is a cross-sectional view of a device 101 and an apparatus 100 that incorporates interposer technology where the first and second interposer springs 118 a and 118 b are not bonded to but are touching the first and second TSVs 104 a and 104 b and the first and second bumps 108 a and 108 b located on the chip 106 of the device 101 according to an embodiment of the invention. When the apparatus 100 is pressed onto the device 101, the TSVs 104 a and 104 b and the first and second bumps 108 a and 108 b are mechanically and electrically connected using the first and second interposer springs 118 a and 118 b and the upper outer bond rings 116 a and 116 b are bonded to the lower outer bond rings 110 a and 110 b.

When the apparatus 100 is spaced apart from (i.e., not touching) the device 101, the first and second interposer springs 118 a and 118 b are positioned along a horizontal plane (see FIG. 1A). When the apparatus 100 is touching the device 101, the first and second interposer springs 118 a and 118 b are bent in an upward direction (see FIG. 1C). As shown in FIG. 1C, the upper outer bond rings 116 a and 116 b are bonded to the lower outer bond rings 110 a and 110 b causing the first and second interposer springs 118 a and 118 b to bend. However, the first and second interposer springs 118 a and 118 b only slightly compress the TSVs 104 a and 104 b and the first and second bumps 108 a and 108 b to make the mechanical and electrical connections. In one embodiment, the mechanical and electrical connections are maintained only by the bending force 124 from the first and second interposer springs 118 a and 118 b and the bonding strength between the upper outer bond rings 116 a and 116 b and the lower outer bond rings 110 a and 110 b. The single bonding between the upper outer bond rings 116 a and 116 b and the lower outer bond rings 110 a and 110 b is advantageous because of the single bonding material and process resulting in a greater reliability, a simpler fabrication process, and a lower production cost. In one embodiment, the first and second interposer springs 118 a and 118 b are designed to provide a sufficient bending force and are not damaged by excessive bending stress.

In one embodiment, only the lower outer bond rings 110 a and 110 b and the upper outer bond rings 116 a and 116 b are bonded together. The remaining components (i.e., the TSVs 104 a and 104 b and the first and second interposer springs 118 a and 118 b, and the first and second bumps 108 a and 108 b and the first and second interposer springs 118 a and 118 b) are not bonded together but are touching one another.

FIGS. 3A-3F are cross-sectional views of a device 301 and an apparatus 300 that incorporates interposer technology according to an embodiment of the invention. The device 301 includes a substrate 302 and a plurality of chips 306, 307 and 309 that are mounted on the substrate 302. The substrate 302 may also be a TSV wafer or a second interposer wafer.

The device 301 may include a substrate 302 or a TSV wafer 302, first and second TSVs 304 a and 304 b, chips 306, 307 and 309, first and second bumps 308 a and 308 b located on the chip 306, first and second bumps 308 c and 308 d located on the chip 307, first and second bumps 308 e and 308 f located on the chip 309, upper bonding pads 316 a and 316 b and/or lower bonding pads 310 a and 310 b. The first and second bumps 308 a and 308 b (or 308 c and 308 d or 308 e and 308 f) may provide electrical connections to the underlying chip 306 (or 307 or 309). As shown in FIG. 3A, the heights or thickness of the chips 306, 307 and 309 are different. In one embodiment, the chips 307 and 309 have the same design but have slightly different heights or thicknesses because of fabrication variations. The bonding pads 320 a, 320 b, 320 c, 320 d, 320 e and 320 f on the interposer springs 318 a, 318 b, 318 c, 318 d, 318 e and 318 f, respectively, are mechanically and electrically connected to the upper bonding pads 310 b and 316 b. After the upper bonding pads 316 a and 316 b are bonded to the lower bonding pads 310 a and 310 b, the bonding pads 320 a, 320 b, 320 c, 320 d, 320 e and 320 f are connected to the bumps 308 a, 308 b, 308 c, 308 d, 308 e and 308 f, respectively, and the TSVs 304 a and 304 b on the substrate 302.

The first and second TSVs 304 a and 304 b are vertical electrical connections which pass completely through the substrate 302. The chips 306, 307 and 309 are mounted on the substrate 302. The bumps 308 a, 308 b, 308 c, 308 d, 308 e and 308 f may be flat, square, curved, round, oval and/or flexible. The first and second bumps 108 a and 108 b may be bonded to the chip 106.

The apparatus 300 may include a spring interposer wafer 312, first and second upper bonding pads 316 a and 316 b, and a plurality of interposer springs 318 connected to a plurality of bonding pads 320. In one embodiment, the plurality of interposer springs 318 are each a cantilevered spring.

By applying the bonding pressure 322, the bonding pads successively touch the bumps on the chips or the TSVs. The differences in heights or thicknesses of the chips 306, 307 and 309 causes the bonding pads 320 to touch the bonding pads 308 at different times. First, the bonding pads 320 a and 320 b touch the bonding pads 308 a and 308 b (see FIG. 3B). Second, the bonding pads 320 c and 320 d touch the bonding pads 308 c and 308 d (see FIG. 3C). Third, the bonding pads 320 e and 320 f touch the bonding pads 308 e and 308 f (see FIG. 3D). Fourth, the upper bonding pads 316 a and 316 b touch the lower bonding pads 310 a and 310 b (see FIG. 3E). Due to the compliance of the interposer springs 318, the spring interposer wafer 312 can move downwards, even though some of the bonding pads 320 are touching the bonding pads 308, until the upper bonding pads 316 a and 316 b come into contact with the lower bonding pads 310 a and 310 b (see FIG. 3E). Then, the appropriate bonding conditions (e.g., temperature, additional pressure, voltage, etc.) are applied to the combined structure shown in FIG. 3E and all the components (i.e., the chips 306, 307 and 309, the TSVs 304 a and 304 b, and the interposer springs (collectively referred as interposer springs 317)) are simultaneously bonded to form the final structure as shown in FIG. 3F.

The bonding conditions may be applied one time or several times depending on the particular application. For example, a different bonding process may be used for chip bonding and TSV bonding. In this example, a first bonding condition may be applied for chip bonding at the step shown in FIG. 3D and a second bonding condition may be applied for TSV bonding at the step shown in FIG. 3E. In one embodiment, only a single bonding can take place, for example, between the upper bonding pads 316 a and 316 b and the lower bonding pads 310 a and 310 b. The interposer springs 317 are designed to be flexible to provide sufficient bonding force without damaging the bonding pads 308.

FIGS. 4A and 4B are cross-sectional views of a semiconductor device 401 and an apparatus 400 that incorporates interposer technology according to an embodiment of the invention. FIGS. 4A and 4B show interposer springs 418 a, 418 b, 418 c and 418 d that are initially tilted or bowed to provide a larger bending force between the interposer springs 418 a, 418 b, 418 c and 418 d and the bumps 408 a, 408 b, 408 c and 408 d and/or the TSVs 404 a and 404 b. The interposer springs 418 a, 418 b, 418 c and 418 d can be tilted or bowed by initiating thermal stress, generating material property mismatches, or applying external forces such as electrostatic or magnetic forces. Each interposer spring 418 a, 418 b, 418 c and 418 d may have a corresponding bonding pad 420 a, 420 b, 420 c and 420 d attached thereto.

Those of ordinary skill would appreciate that the various illustrative logical blocks, modules, and algorithm steps described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed apparatus and methods.

The previous description of the disclosed examples is provided to enable any person of ordinary skill in the art to make or use the disclosed methods and apparatus. Various modifications to these examples will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other examples without departing from the spirit or scope of the disclosed method and apparatus. The described embodiments are to be considered in all respects only as illustrative and not restrictive and the scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope. 

1. An apparatus for integrating multiple devices, comprising: a substrate having a first via and a second via; a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via; first and second bumps positioned on the semiconductor chip; and an interposer wafer having a first interposer spring and a first electrical connection attached to the first interposer spring, the first electrical connection being in contact with the first via and the first bump and providing an electrical connection between the first via and the first bump, and a second interposer spring and a second electrical connection attached to the second interposer spring, the second electrical connection being in contact with the second via and the second bump and providing an electrical connection between the second via and the second bump.
 2. The apparatus of claim 1 wherein the substrate is a through-silicon via wafer.
 3. The apparatus of claim 1 wherein the first via and the second via are vertical electrical connections that pass completely through the substrate.
 4. The apparatus of claim 1 wherein the first and second bumps are bonded to the semiconductor chip and provide an electrical connection to the semiconductor chip.
 5. The apparatus of claim 1 wherein the first and second interposer springs are cantilevered springs.
 6. The apparatus of claim 1 wherein the first and second interposer springs are formed in the shape of a cantilevered bridge L shape.
 7. The apparatus of claim 1 wherein the first interposer spring is bent to provide the first electrical connection between the first via and the first bump and the second interposer spring is bent to provide the second electrical connection between the second via and the second bump.
 8. The apparatus of claim 1 further comprising: a lower bond ring attached to an outer top portion of the substrate; and an upper bond ring attached to an outer bottom portion of the interposer wafer.
 9. The apparatus of claim 8 wherein the first and second interposer springs are bent when the upper bond ring is attached to the lower bond ring.
 10. The apparatus of claim 1 further comprising a pressure device to exert a downward force on the interposer wafer, the downward force being greater than a bending force of each interposer spring and less than a fracture force of each interposer spring.
 11. An apparatus for integrating multiple devices, comprising: a substrate having a first via and a second via; a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via; first and second bumps positioned on the semiconductor chip; and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, the first electrical connection being in contact with the first via and the first bump and providing an electrical connection between the first via and the first bump, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring, the second electrical connection being in contact with the second via and the second bump and providing an electrical connection between the second via and the second bump.
 12. The apparatus of claim 11 wherein the substrate is a through-silicon via wafer.
 13. The apparatus of claim 11 wherein the first via and the second via are vertical electrical connections that pass completely through the substrate.
 14. The apparatus of claim 11 wherein the first and second bumps are bonded to the semiconductor chip and provide an electrical connection to the semiconductor chip.
 15. The apparatus of claim 11 wherein the first and second interposer springs are cantilevered springs.
 16. The apparatus of claim 11 wherein the first and second interposer springs are formed in the shape of a cantilevered bridge L shape.
 17. The apparatus of claim 11 wherein the first interposer spring is bent to provide the first electrical connection between the first via and the first bump and the second interposer spring is bent to provide the second electrical connection between the second via and the second bump.
 18. The apparatus of claim 11 further comprising: a lower bond ring attached to an outer top portion of the substrate; and an upper bond ring attached to an outer bottom portion of the interposer wafer.
 19. The apparatus of claim 18 wherein the first and second interposer springs are bent when the upper bond ring is attached to the lower bond ring.
 20. The apparatus of claim 11 further comprising a pressure device to exert a downward force on the interposer wafer, the downward force being greater than a bending force of each interposer spring and less than a fracture force of each interposer spring. 